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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [utils/] [setup/] [configure.sh] - Rev 116

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Rev	Log message	Author	Age	Path
115	configure.sh script dir aware. minsoc-install.sh logging to script dir.	rfajardo	4793d 21h	/minsoc/branches/rc-1.0/utils/setup/configure.sh
113	minsoc-install.sh & minsoc-configure.sh: -aware of location of configure.sh script configure.sh: -does not block on patch error spartan3e_starter_kit & spartan3e_starter_kit_eth: -or1200_defines.v updated prj: -src/blackboxes/or1200_top.v adjusted to or1200_rel1 -Makefile had a typo regarding altera vhdl files	rfajardo	4793d 22h	/minsoc/branches/rc-1.0/utils/setup/configure.sh
112	Updating installation & configuration scripts.	rfajardo	4794d 13h	/minsoc/branches/rc-1.0/utils/setup/configure.sh
110	Fixing several minor issues with the system: -minsoc-install splitted into installation and configuration -minsoc-configure.sh can be used to configure a fresh checked out system -configure script used by both minsoc-configure.sh and minsoc-install.sh to configure -rtl/verilog: svn externals fixed -or1200 rolled back to release-1.0 -prj/scripts: -Makefile has been used by simulation to differentiate project definition of vhdl and verilog files -Altera was differentiating it in script -now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation. -altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files. -prj/src: or1200_top.prj downdated to definition of or1200_v1	rfajardo	4794d 14h	/minsoc/branches/rc-1.0/utils/setup/configure.sh

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