| Rev |
Log message |
Author |
Age |
Path |
| 139 |
Creating a verilator branche. |
rfajardo |
4768d 01h |
/minsoc/branches/verilator/backend/std/minsoc_defines.v |
| 109 |
Creating a branche for release candidate 1.0. |
rfajardo |
4794d 15h |
/minsoc/branches/verilator/backend/std/minsoc_defines.v |
| 64 |
firmware makefiles:
-every firmware makefile has now complete dependency. This also includes dependency on files under minsoc/backend (target specific files). That means, that if some target specific header changes, the support library dependent on it will be compiled. That will always happen, even if you compile the uart firmware. In other words, if you want to use uart firmware, you can always simply compile uart by issuing make all. If anything has changed, backend files, support library, drivers, it will update everything for you.
-TODO: dependency can be automatic created by using make together with gcc. Use it instead of declaring all dependencies manually.
Makefile system for synthesis:
-the dependency for every implementation step has been checked and is working fine.
-Makefile plus support files have been moved to minsoc/syn/src
-make usage is still under syn through files generated by backend bashscripts
Backend:
-files under backend are target specific files used for the system to work
-firmware compilation
-system simulation
-system implementation
-This directory is populated by visiting one of its subdirectories and typing ./configure
backend/spartan3a_dsp_kit:
-working on FPGA
backend/spartan3e_starter_kit:
-has to be tested
backend/ml509:
-missing files have to be copied and adapted, configure script has to be copied and adapted
backend/std:
-include files necessary for firmware compilation and system configuration
-it does not include files for synthesis and is not synthesizable |
rfajardo |
4971d 00h |
/minsoc/branches/verilator/backend/std/minsoc_defines.v |
| 63 |
Adding a functional synthesis Makefile system. Still needs a reviews and enhancements, but at least it is something. |
rfajardo |
4974d 18h |
/minsoc/branches/verilator/backend/std/minsoc_defines.v |
| 58 |
Standard definitions depended on implementation order. Now, this should be solved.
minsoc_bench_defines.v: when setting reset to be positive (`define POSITIVE_RESET), NEGATIVE_RESET is undefined. This override the implementation order, so that independent of it, POSITIVE_RESET will be used.
minsoc_defines.v: when setting GENERIC_FPGA, FPGA_TAP and FPGA_CLOCK_DIVISION are undefined. This way, even if FPGA_TAP would come prior to GENERIC_TAP on the correspondent implementation, GENERIC_TAP would still be selected.
IMPORTANT: GENERIC_MEMORY must still be implemented first on minsoc_onchip_ram.v, because FPGA's memory is automatically selected from other definitions and cannot be undefined a priori. Since some other memory types can be selected, there is no trivial solution. However, this shouldn't be a big problem, since the beginning of this file will probably not be modified. |
rfajardo |
4975d 13h |
/minsoc/branches/verilator/backend/std/minsoc_defines.v |
| 57 |
If a FPGA manufacturer is selected, the FPGA families of other manufacturers are automatically ignored.
Some updated to comments.
CLOCK_DIVISOR back to 5. The number does not matter much, but 1 is a bad standard number, since it should never be selected. Comment says, use NO_CLOCK_DIVISION instead.
Changing standard FPGA back to Xilinx and Spartan3A. I'm only doing this because the synthesis examples page of wiki still assume this FPGA to be standardly selected. |
rfajardo |
4975d 14h |
/minsoc/branches/verilator/backend/std/minsoc_defines.v |
| 56 |
Macros for all Altera family devices and pll instantiation |
javieralso |
4982d 12h |
/minsoc/branches/verilator/backend/std/minsoc_defines.v |
| 52 |
Altera ALTPLL Megafunction Instantiation |
javieralso |
4992d 14h |
/minsoc/branches/verilator/backend/std/minsoc_defines.v |
| 20 |
minsoc_defines.v had a semicolon at the end of the two reset polarity definitions.
minsoc_top had a signal array for two different signals which was for backward compatibility. The compatible debugging module is so old that there is no reason for keeping it.
Documentation has been updated to better explain how to use the definitions files, minsoc_defines.v and or1200_defines.v. An example for Altera devices has been added too. |
rfajardo |
5437d 21h |
/minsoc/branches/verilator/backend/std/minsoc_defines.v |
| 7 |
Some changes:
-wb_cabs removed from minsoc_top.v and minsoc_tc_top.v
-added reset polarity control to minsoc_defines.v through:
-POSITIVE_RESET
-NEGATIVE_RESET
-minsoc_onchip_ram_top.v does not use
minsoc_onchip_ram.v oe signals (output enable) anymore,
which are implemented as tristate buffers. Now
minsoc_onchip_ram_top.v has a generated MUX, which
has an arbitrary number of inputs and 1 output.
Input are the internal output of the onchip_rams,
output the wb_dat_o. |
rfajardo |
5548d 19h |
/minsoc/branches/verilator/backend/std/minsoc_defines.v |
| 2 |
First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit |
rfajardo |
5562d 23h |
/minsoc/branches/verilator/backend/std/minsoc_defines.v |
