URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [sim/] [modelsim/] [run_sim.sh] - Rev 139

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4756d 00h	/minsoc/branches/verilator/sim/modelsim/run_sim.sh
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4771d 01h	/minsoc/branches/verilator/sim/modelsim/run_sim.sh
132	ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench.	rfajardo	4774d 20h	/minsoc/branches/verilator/sim/modelsim/run_sim.sh
109	Creating a branche for release candidate 1.0.	rfajardo	4782d 15h	/minsoc/branches/verilator/sim/modelsim/run_sim.sh
70	Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it. Removing timescale definition of minsoc_bench_defines.v files. Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed: -pli ../../bench/verilog/vpi/jp-io-vpi.so to: -pli ../../bench/verilog/vpi/jp-io-vpi.dll These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.	rfajardo	4952d 00h	/minsoc/branches/verilator/sim/modelsim/run_sim.sh