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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [periph/] [omsp_timerA_defines.v] - Rev 119

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117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4919d 18h /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA_defines.v
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 5009d 15h /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA_defines.v

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