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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [run/] [run] - Rev 122

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122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4803d 19h /openmsp430/trunk/core/sim/rtl_sim/run/run
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4941d 19h /openmsp430/trunk/core/sim/rtl_sim/run/run
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4997d 18h /openmsp430/trunk/core/sim/rtl_sim/run/run
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5231d 20h /openmsp430/trunk/core/sim/rtl_sim/run/run
67 Added 16x16 Hardware Multiplier. olivier.girard 5381d 04h /openmsp430/trunk/core/sim/rtl_sim/run/run
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5630d 18h /openmsp430/trunk/core/sim/rtl_sim/run/run

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