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[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board/] [bench/] [verilog/] [msp_debug.v] - Rev 221

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Rev	Log message	Author	Age	Path
221	Move old Altera-DE1 project to the OBSOLETE directory. Create new Altera-DE0-Nano-SoC project, also containing a small demo of the openGFX430 graphic controller.	olivier.girard	3026d 02h	/openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/verilog/msp_debug.v
136	Update all FPGA projects with the latest core version.	olivier.girard	4635d 02h	/openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/verilog/msp_debug.v
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4942d 03h	/openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/verilog/msp_debug.v
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	5017d 03h	/openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/verilog/msp_debug.v
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	5027d 03h	/openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/verilog/msp_debug.v
29	Add Altera Cyclone II FPGA project example.	olivier.girard	5451d 03h	/openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/verilog/msp_debug.v

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