URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board/] [bench/] [verilog/] [registers.v] - Rev 221

Rev	Log message	Author	Age	Path
221	Move old Altera-DE1 project to the OBSOLETE directory. Create new Altera-DE0-Nano-SoC project, also containing a small demo of the openGFX430 graphic controller.	olivier.girard	3115d 23h	/openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/verilog/registers.v
143	Update FPGA software examples to support MSPGCC Uniarch.	olivier.girard	4677d 01h	/openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/verilog/registers.v
136	Update all FPGA projects with the latest core version.	olivier.girard	4725d 00h	/openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/verilog/registers.v
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	5032d 00h	/openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/verilog/registers.v
39	Update FPGA projects with new openMSP430 core.	olivier.girard	5539d 00h	/openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/verilog/registers.v
29	Add Altera Cyclone II FPGA project example.	olivier.girard	5541d 01h	/openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/bench/verilog/registers.v