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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_frontend.v] - Rev 109

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Rev	Log message	Author	Age	Path
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4998d 07h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	5014d 22h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	5018d 23h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	5032d 23h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v
85	Diverse RTL cosmetic updates.	olivier.girard	5055d 22h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v
61	Update openMSP430 rtl.	olivier.girard	5414d 21h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v
54	Update FPGA projects with the combinatorial loop fixed.	olivier.girard	5422d 01h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v
37		olivier.girard	5450d 22h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v
34	To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.	olivier.girard	5451d 00h	/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5451d 01h	/openmsp430/trunk/core/rtl/verilog/frontend.v
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5572d 02h	/openmsp430/trunk/core/rtl/verilog/frontend.v
17	Updated header with SVN info	olivier.girard	5597d 22h	/openmsp430/trunk/core/rtl/verilog/frontend.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5632d 22h	/openmsp430/trunk/core/rtl/verilog/frontend.v

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