URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [branches/] [or1200_rel3/] [rtl/] [verilog/] [or1200_cpu.v] - Rev 852

Rev	Log message	Author	Age	Path
795	Created or1200_rel3 branch from rev 794	olof	4603d 23h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_cpu.v
642	or1200: add carry, overflow bits, and range exception	julius	4838d 22h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_cpu.v
640	or1200: add l.ext instructions, fix a MAC bug	julius	4838d 22h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_cpu.v
481	OR1200 Update. RTL and spec.	julius	5064d 14h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_cpu.v
401	Fixing find first one (ff1) and find last one (fl1) support in OR1200. Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported instructions table.	julius	5143d 03h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_cpu.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5205d 18h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_cpu.v
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5256d 01h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_cpu.v
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5256d 02h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_cpu.v
141	added OpenRISC version rel3	marcus.erlandsson	5267d 06h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_cpu.v
10	or1200 added from or1k subversion repository	unneback	5668d 09h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_cpu.v