OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [or32/] [wrapper.c] - Rev 350

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
244 Don't try to skip prologue using SAL info (fails with STABS). Fuller check of prologue. Change register names to rnn from gprnn to match assembler. Add debug option to simulator wrapper.

* or32-tdep.c (or32_register_name): Changed to rnn rather than
gprnn to mach the assembler.
(or32_is_arg_reg, or32_is_callee_saved_reg): Added.
(or32_skip_prologue): Don't use skip_prologue_using_sal. Check for
argument as well as callee saved registers in prologue.
(or32_frame_cache):Check for argument as well as callee saved
registers in prologue.

* wrapper.c: OR32_SIM_DEBUG added to control debug messages.
(sim_close, sim_load, sim_create_inferior, sim_fetch_register)
(sim_stop): Debug statement added.
(sim_read, sim_write): Debug statements now controlled by
OR32_SIM_DEBUG.
(sim_store_register, sim_resume): Debug statement added and
existing debug statements now controlled by OR32_SIM_DEBUG.
jeremybennett 5215d 00h /openrisc/trunk/gnu-src/gdb-7.1/sim/or32/wrapper.c
237 Fixes bug in handling single stepping. jeremybennett 5230d 17h /openrisc/trunk/gnu-src/gdb-7.1/sim/or32/wrapper.c
232 Brought documentation up to date. jeremybennett 5232d 21h /openrisc/trunk/gnu-src/gdb-7.1/sim/or32/wrapper.c
227 GDB 7.1 for OpenRISC 1000. Initial checkin. jeremybennett 5234d 14h /openrisc/trunk/gnu-src/gdb-7.1/sim/or32/wrapper.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.