OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 729

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
643 or1200: new ALU comparision implementation option, TLB invalidate register indicated as not present, multiply overflow detection bug fix julius 4839d 01h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
642 or1200: add carry, overflow bits, and range exception julius 4839d 01h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
640 or1200: add l.ext instructions, fix a MAC bug julius 4839d 01h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
481 OR1200 Update. RTL and spec. julius 5064d 17h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
401 Fixing find first one (ff1) and find last one (fl1) support in OR1200.

Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported
instructions table.		 julius 5143d 05h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5193d 02h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5195d 10h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
259 Fixing or1200_defines FPU module selection defines - They are no longer needed julius 5205d 20h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5205d 20h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5256d 04h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
141 added OpenRISC version rel3 marcus.erlandsson 5267d 08h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
10 or1200 added from or1k subversion repository unneback 5668d 11h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.