OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_reg2mem.v] - Rev 851

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.
julius 5192d 23h /openrisc/trunk/or1200/rtl/verilog/or1200_reg2mem.v
141 added OpenRISC version rel3 marcus.erlandsson 5267d 06h /openrisc/trunk/or1200/rtl/verilog/or1200_reg2mem.v
10 or1200 added from or1k subversion repository unneback 5668d 09h /openrisc/trunk/or1200/rtl/verilog/or1200_reg2mem.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.