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[/] [openrisc/] [trunk/] [or1ksim/] [configure] - Rev 300

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236 Terminate execution on NOP_EXIT, even if debugging, add support for RSP qAttached packet, stall in library after single instruction is ST bit is set in SPR DMR1. Fix softfloat to allow compilation with -O0 for debugging.

* configure: Regenerated.
* configure.ac: Version changed to current date. Test for
varargs.h dropped.
* cpu/or32/insnset.c <l_nop>: Terminate execution on NOP_EXIT,
even if debugging.
* debug/rsp-server.c (rsp_query): Added support for qAttached
packet.
* libtoplevel.c (or1ksim_run): Stall after a single instruction if
SPR_DMR1_ST flag is set.
* softfloat/host.h: Make #define of INLINE conditional, to allow
the user to override.
* softfloat/README: Added instructions for non-optimized compilation.
* softfloat/softfloat-macros: Add a conditional #ifndef
NO_SOFTFLOAT_UNUSUED around unused functions.
jeremybennett 5242d 16h /openrisc/trunk/or1ksim/configure
235 Removed support for old OpenRISC JTAG Remote Protocol. jeremybennett 5242d 21h /openrisc/trunk/or1ksim/configure
234 Minor tidy ups. DOS end of line chars fixed. jeremybennett 5243d 22h /openrisc/trunk/or1ksim/configure
233 New softfloat FPU and testfloat sw for or1ksim julius 5244d 09h /openrisc/trunk/or1ksim/configure
230 Changed library interface. Fixed namespace problems with instruction lookup in library.

* configure: Regenerated.
* configure.ac: Version changed to current date.
* cpu/or1k/opcode/or32.h <or1ksim_build_automata>: Renamed from
build_automata.
<l_none, num_opcodes, insn_index>: Deleted.
<or1ksim_op_start>: Renamed from op_start.
<or1ksim_automata>: Renamed from automata.
<or1ksim_ti>: Renamed from ti.
<or1ksim_or32_opcodes>: Renamed from or32_opcodes.
<or1ksim_disassembled>: Renamed from disassembled.
<or1ksim_insn_len>: Renamed from insn_len.
<or1ksim_insn_name>: Renamed from insn_name.
<or1ksim_destruct_automata>: Renamed from destruct_automata.
<or1ksim_insn_decode>: Renamed from insn_decode.
<or1ksim_disassemble_insn>: Renamed from disassemble_insn.
<or1ksim_disassemble_index>: Renamed from disassemble_index.
<or1ksim_extend_imm>: Renamed from extend_imm.
<or1ksim_or32_extract>: Renamed from or32_extract
* cpu/or32/or32.c, cpu/or32/execute.c, cpu/or32/generate.c,
* cpu/common/stats.c, cpu/common/abstract.c, cpu/common/parse.c,
* cpu/or1k/opcode/or32.h, cuc/load.c, cuc/cuc.c,
* support/dumpverilog.c, toplevel-support.c: Renaming
corresponding to changes in cpu/or1k/opcode/or32.h.
* cpu/or32/execute-fp.h: Deleted
* cpu/or32/generate.c <include_strings>: Remove reference to
execute-fp.h
* cpu/or32/execute.c <host_fp_rm>: Declared static.
(fp_set_flags_restore_host_rm, fp_set_or1k_rm): Declared static,
forward declaration removed.
* or1ksim.h (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
* libtoplevel.c (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
jeremybennett 5245d 14h /openrisc/trunk/or1ksim/configure
226 Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated julius 5247d 14h /openrisc/trunk/or1ksim/configure
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5247d 22h /openrisc/trunk/or1ksim/configure
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5254d 13h /openrisc/trunk/or1ksim/configure
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5277d 18h /openrisc/trunk/or1ksim/configure
134 Updates for stable release 0.4.0 jeremybennett 5285d 22h /openrisc/trunk/or1ksim/configure
127 New config option to allow l.xori with unsigned operand. jeremybennett 5291d 18h /openrisc/trunk/or1ksim/configure
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5292d 14h /openrisc/trunk/or1ksim/configure
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5292d 18h /openrisc/trunk/or1ksim/configure
122 Added l.ror and l.rori with associated tests. jeremybennett 5293d 14h /openrisc/trunk/or1ksim/configure
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5293d 14h /openrisc/trunk/or1ksim/configure
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5294d 11h /openrisc/trunk/or1ksim/configure
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5296d 14h /openrisc/trunk/or1ksim/configure
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5297d 14h /openrisc/trunk/or1ksim/configure
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5298d 14h /openrisc/trunk/or1ksim/configure
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5301d 15h /openrisc/trunk/or1ksim/configure

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