URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Rev 530

Rev	Log message	Author	Age	Path
508	Updates for Or1ksim 0.5.0rc3.	jeremybennett	4986d 05h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	5114d 16h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c
432	Updates to handle interrupts correctly.	jeremybennett	5119d 01h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c
430	or1ksim - clarifying interrupt behavior in code and documentation.	julius	5121d 22h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c
226	Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated	julius	5236d 22h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5309d 01h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5668d 07h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c