URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [OrpsocAccess.h] - Rev 79

Rev	Log message	Author	Age	Path
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5421d 08h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5438d 06h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5539d 05h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5557d 22h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5609d 09h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
6	Checking in ORPSoCv2	julius	5671d 21h	/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h