URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [mt48lc16m16a2.v] - Rev 656

Rev	Log message	Author	Age	Path
495	ORPSoC adding more accessor functions to Micron SDRAM model.	julius	5017d 05h	/openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5142d 21h	/openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5609d 07h	/openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v
6	Checking in ORPSoCv2	julius	5671d 19h	/openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v