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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [orpsoc_testbench.v] - Rev 465

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Rev	Log message	Author	Age	Path
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5142d 23h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
397	ORPSoCv2: doc/ path added, with Texinfo documentation. Still a work in progress. VPI files updated. OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction. Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.	julius	5145d 05h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5195d 01h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5197d 00h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5557d 22h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5609d 09h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5653d 09h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
6	Checking in ORPSoCv2	julius	5671d 21h	/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v

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