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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] [orpsoc-defines.v] - Rev 741

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506 ORPSoC or1200 interrupt and syscall generation test julius 4993d 08h /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 5136d 08h /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5143d 03h /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 5145d 09h /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5193d 15h /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
361 OPRSoCv2 - adding things left out in last check-in julius 5195d 05h /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v

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