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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ic_ram.v] - Rev 766

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Rev Log message Author Age Path
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.
julius 5079d 01h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 5079d 18h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5205d 13h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
350 Adding new OR1200 processor to ORPSoCv2 julius 5208d 17h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ic_ram.v

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