URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ic_ram.v] - Rev 526

Rev	Log message	Author	Age	Path
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	5069d 12h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
476	ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.	julius	5070d 05h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5196d 00h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5199d 04h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ic_ram.v