| Rev |
Log message |
Author |
Age |
Path |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5429d 08h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5439d 05h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5481d 01h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5486d 05h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5496d 22h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5507d 05h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5525d 05h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5540d 04h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5558d 22h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5610d 08h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5634d 05h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5650d 02h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5654d 09h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 36 |
Better clean rule in makefile |
julius |
5668d 09h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 6 |
Checking in ORPSoCv2 |
julius |
5672d 20h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
