OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [ethmac/] [sim/] [ethmac-rx.c] - Rev 811

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 5119d 03h /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.
julius 5151d 05h /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.
julius 5152d 05h /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c
395 ORPSoCv2 moving ethernet tests to correct place julius 5159d 04h /openrisc/trunk/orpsocv2/sw/tests/eth/sim/eth-rx.c
349 ORPSoCv2 update with new software and makefile update julius 5209d 05h /eth-rx.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.