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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-except.S] - Rev 449

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426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...
julius 5138d 12h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.
julius 5138d 13h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 5150d 11h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 5158d 22h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 5191d 21h /or1200-except.S
349 ORPSoCv2 update with new software and makefile update julius 5208d 23h /or1200-except.S

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