URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-simple.c] - Rev 805

Rev	Log message	Author	Age	Path
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5148d 03h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-simple.c
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5196d 23h	/or1200-simple.c
349	ORPSoCv2 update with new software and makefile update	julius	5198d 03h	/or1200-simple.c