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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [cache/] [Makefile.in] - Rev 1772

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1765 root 5744d 12h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in
1378 aclocal && autoconf && automake phoenix 7217d 22h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7233d 00h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in
1249 Downgrading back to automake-1.4 lampret 7604d 11h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in
1099 cvs bug fixed markom 8033d 23h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in
970 Testbench is now running on ORP architecture platform. simons 8143d 13h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in
876 Beta release of ATA simulation rherveille 8187d 12h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in
517 some performance optimizations markom 8366d 20h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in
221 major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup markom 8439d 00h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in
84 Update. lampret 8644d 21h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in
18 or16 added, or1k renamed to or32. lampret 8978d 02h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in
13 Rebuild of the generated files. jrydberg 9038d 19h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in
7 Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support.		 jrydberg 9038d 19h /or1k/branches/stable_0_1_x/or1ksim/cache/Makefile.in

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