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[/] [plasma/] [trunk/] [vhdl/] [mlite_pack.vhd] - Rev 370

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Rev Log message Author Age Path
352 linus 5726d 10h /plasma/trunk/vhdl/mlite_pack.vhd
350 root 5755d 05h /plasma/trunk/vhdl/mlite_pack.vhd
346 Support optional 4KB cache rhoads 5823d 00h /plasma/trunk/vhdl/mlite_pack.vhd
332 Updated Altera lpm_ram_dp rhoads 5883d 19h /plasma/trunk/vhdl/mlite_pack.vhd
285 Added eth_dma rhoads 6162d 19h /plasma/trunk/vhdl/mlite_pack.vhd
264 Latch address and byte_we in mem_ctrl.vhd rhoads 6206d 03h /plasma/trunk/vhdl/mlite_pack.vhd
202 Defined outputing PC as stage #0 rhoads 6445d 05h /plasma/trunk/vhdl/mlite_pack.vhd
194 Implemented BREAK and SYSCALL opcodes rhoads 6510d 01h /plasma/trunk/vhdl/mlite_pack.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6855d 18h /plasma/trunk/vhdl/mlite_pack.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7335d 16h /plasma/trunk/vhdl/mlite_pack.vhd
128 Reset all registers, constants now upper case. rhoads 7473d 03h /plasma/trunk/vhdl/mlite_pack.vhd
125 Fixed pc_source_type comment. rhoads 7491d 17h /plasma/trunk/vhdl/mlite_pack.vhd
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7672d 17h /plasma/trunk/vhdl/mlite_pack.vhd
96 Simplify take_branch rhoads 8195d 21h /plasma/trunk/vhdl/mlite_pack.vhd
91 Removed unused alu_function_type entries rhoads 8197d 14h /plasma/trunk/vhdl/mlite_pack.vhd
70 pipeline rhoads 8205d 16h /plasma/trunk/vhdl/mlite_pack.vhd
62 updated LPM functions; mem_none->mem_fetch rhoads 8213d 21h /plasma/trunk/vhdl/mlite_pack.vhd
50 Update prototypes rhoads 8224d 16h /plasma/trunk/vhdl/mlite_pack.vhd
47 Altera rhoads 8231d 17h /plasma/trunk/vhdl/mlite_pack.vhd
44 Fixed signed 64-bit multiply rhoads 8309d 06h /plasma/trunk/vhdl/mlite_pack.vhd

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