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[/] [raytrac/] [branches/] [fp/] [doc/] [dsgn062012.xlsx] - Rev 206

Rev	Log message	Author	Age	Path
199	Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work	jguarin2002	4522d 10h	/raytrac/branches/fp/doc/dsgn062012.xlsx
197	Chnages on interconnectivity: Check out the SGDMA Sheets	jguarin2002	4532d 11h	/raytrac/branches/fp/doc/dsgn062012.xlsx
196	raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues	jguarin2002	4535d 22h	/raytrac/branches/fp/doc/dsgn062012.xlsx
195	Document advance and changes in the design	jguarin2002	4538d 19h	/raytrac/branches/fp/doc/dsgn062012.xlsx
192	Some change I dont realize what is it in the design document (xls)	jguarin2002	4555d 09h	/raytrac/branches/fp/doc/dsgn062012.xlsx
180	Documentos de diseño y documento final	jguarin2002	4562d 09h	/raytrac/branches/fp/doc/dsgn062012.xlsx