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[/] [reed_solomon_decoder/] [trunk/] [rtl/] [input_syndromes.v] - Rev 2

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2 Initial commit of Reed Solomon Decoder Verilog core (204,188,8)
corrects up to 8 errors per block
Pipelined and verfied on FPGA
aelmahmoudy 5619d 06h /reed_solomon_decoder/trunk/rtl/input_syndromes.v

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