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[/] [reed_solomon_decoder/] [trunk/] [simulation/] [RS_test_vectors.m] - Rev 4

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2 Initial commit of Reed Solomon Decoder Verilog core (204,188,8)
corrects up to 8 errors per block
Pipelined and verfied on FPGA
aelmahmoudy 5626d 07h /reed_solomon_decoder/trunk/simulation/RS_test_vectors.m

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