URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_core.sv] - Rev 71

Rev	Log message	Author	Age	Path
70	Warning Cleanup	dinesha	4236d 20h	/sdr_ctrl/trunk/verif/tb/tb_core.sv
68	SDRAM Address bit increased from 12 bit to 13 bit	dinesha	4236d 21h	/sdr_ctrl/trunk/verif/tb/tb_core.sv
56	FPGA Synth optimisation	dinesha	4674d 20h	/sdr_ctrl/trunk/verif/tb/tb_core.sv
53	Test bench upgradation	dinesha	4678d 18h	/sdr_ctrl/trunk/verif/tb/tb_core.sv
49	clean up	dinesha	4681d 21h	/sdr_ctrl/trunk/verif/tb/tb_core.sv
48	top-level cleanup	dinesha	4681d 22h	/sdr_ctrl/trunk/verif/tb/tb_core.sv
46	test bench upgrade + rtl cleanup	dinesha	4683d 22h	/sdr_ctrl/trunk/verif/tb/tb_core.sv
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4684d 03h	/sdr_ctrl/trunk/verif/tb/tb_core.sv
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4686d 01h	/sdr_ctrl/trunk/verif/tb/tb_core.sv
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4686d 02h	/sdr_ctrl/trunk/verif/tb/tb_core.sv
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4690d 20h	/sdr_ctrl/trunk/verif/tb/tb_core.sv