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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_startup/] [spi_flash_shift.v] - Rev 47

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42 Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it. julius 5697d 14h /test_project/trunk/rtl/verilog/components/or1k_startup/spi_flash_shift.v
19 the rest of the design unneback 5704d 23h /test_project/trunk/rtl/verilog/components/or1k_startup/spi_shift.v

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