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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [wb_sdram_ctrl/] [wb_sdram_ctrl.v] - Rev 42

Rev	Log message	Author	Age	Path
42	Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it.	julius	5688d 01h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl.v
38	Actually that last fix caused another bug. This, and the original, are now fixed. Dhrystone ICDC passes	julius	5688d 08h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
37	Hacked a bug fix - probably due to DCache bugs which are due to be fixed - dhrystone-icdc test still does not complete	julius	5689d 05h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
22	compiles with icarus. basic make script done	julius	5694d 11h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
18	the rest of the design	unneback	5695d 10h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v