OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [sw/] [mul/] [Makefile] - Rev 58

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
52 Enabled own printf function using UART as output julius 5672d 22h /test_project/trunk/sw/mul/Makefile
45 Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default julius 5679d 03h /test_project/trunk/sw/mul/Makefile
33 Fixed up software linker script, and changed placement of vectors where necessary. Icarus tests up to mul-nocache-O2 works but had to re-enable MAC in or1200 julius 5688d 21h /test_project/trunk/sw/mul/Makefile
25 Adding sw dir PROPERLY julius 5692d 12h /test_project/trunk/sw/mul/Makefile

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.