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[/] [versatile_mem_ctrl/] [trunk/] [syn/] [altera/] [bin/] [versatile_memory_controller.tcl] - Rev 66

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Rev Log message Author Age Path
20 Minor update of sdc-file. mikaeljf 5412d 18h /versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.tcl
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5423d 19h /versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.tcl

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