URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_risc.v] - Rev 47

Rev	Log message	Author	Age	Path
47	Fix status bit error in ADC and SBC instruction, fix error in thread startup.	rehayes	5437d 00h	/xgate/trunk/rtl/verilog/xgate_risc.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5471d 23h	/xgate/trunk/rtl/verilog/xgate_risc.v
40	Update for single program counter adder	rehayes	5492d 02h	/xgate/trunk/rtl/verilog/xgate_risc.v
34	minor changes related to wishbone master interface	rehayes	5500d 04h	/xgate/trunk/rtl/verilog/xgate_risc.v
31	Cleanup for MAX_CHANNEL bus	rehayes	5511d 23h	/xgate/trunk/rtl/verilog/xgate_risc.v
26	Add synopsys commands, add else defaults for semphore state machine.	rehayes	5527d 00h	/xgate/trunk/rtl/verilog/xgate_risc.v
17	Additions for XGCHID debug commands	rehayes	5532d 23h	/xgate/trunk/rtl/verilog/xgate_risc.v
15	Fix R1 load at boot up, add debug features	rehayes	5545d 21h	/xgate/trunk/rtl/verilog/xgate_risc.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5546d 23h	/xgate/trunk/rtl/verilog/xgate_risc.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5559d 23h	/xgate/trunk/rtl/verilog/xgate_risc.v
2	Initial Checkin	rehayes	5567d 21h	/xgate/trunk/rtl/verilog/xgate_risc.v