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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbm_bus.v] - Rev 28

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12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5546d 23h /xgate/trunk/rtl/verilog/xgate_wbm_bus.v

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