URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [cpudefs.v] - Rev 83

Rev	Log message	Author	Age	Path
72	Sets XULA25 as the default.	dgisselq	3097d 10h	/xulalx25soc/trunk/rtl/cpu/cpudefs.v
52	This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and prepares it for the 32x32 bit multiply instruction set change.	dgisselq	3145d 10h	/xulalx25soc/trunk/rtl/cpu/cpudefs.v
46	This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v from working when long pipelined reads were interrupted by the necessity of a pair of refresh cycles.	dgisselq	3175d 13h	/xulalx25soc/trunk/rtl/cpu/cpudefs.v
31	A bug fix, although one that rearranges the bus. The first four I/O locations have been adjusted. The new locations are reflected in wishbone.html. In addition, the PWM and UART devices no longer create bus errors when accessed. Finally, this version uses a `define XULA25 to determine whether or not to build for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define would be to place it into your Xilinx configuration, should you wish to build for the LX25.	dgisselq	3187d 12h	/xulalx25soc/trunk/rtl/cpu/cpudefs.v
2	A very first, albeit incomplete, build.	dgisselq	3258d 08h	/xulalx25soc/trunk/rtl/cpu/cpudefs.v