URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [zipbones.v] - Rev 48

Rev	Log message	Author	Age	Path
31	A bug fix, although one that rearranges the bus. The first four I/O locations have been adjusted. The new locations are reflected in wishbone.html. In addition, the PWM and UART devices no longer create bus errors when accessed. Finally, this version uses a `define XULA25 to determine whether or not to build for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define would be to place it into your Xilinx configuration, should you wish to build for the LX25.	dgisselq	3187d 10h	/xulalx25soc/trunk/rtl/cpu/zipbones.v