URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [cpp/] [memsim.h] - Rev 96

Rev	Log message	Author	Age	Path
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3266d 19h	/zipcpu/trunk/bench/cpp/memsim.h
36	Lots of changes to increase processing speed and remove pipeline stalls. Removed the useless flash cache, replacing it with a proper DMA controller. "make test" in the main directory now runs a test program in Verilator and reports on the results.	dgisselq	3359d 22h	/zipcpu/trunk/bench/cpp/memsim.h
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3415d 13h	/zipcpu/trunk/bench/cpp/memsim.h