| Rev |
Log message |
Author |
Age |
Path |
| 167 |
Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache. |
dgisselq |
3069d 15h |
/zipcpu/trunk/doc/src/spec.tex |
| 139 |
Changes necessary to document the changed instruction set: LDIHI became MPY,
and MPYU and MPYS became MPYUHI and MPYSHI respectively. See the specification
for more details. |
dgisselq |
3140d 20h |
/zipcpu/trunk/doc/src/spec.tex |
| 92 |
Adjustments made to match the simplified early branching. |
dgisselq |
3239d 13h |
/zipcpu/trunk/doc/src/spec.tex |
| 73 |
Documentations updates. |
dgisselq |
3270d 15h |
/zipcpu/trunk/doc/src/spec.tex |
| 69 |
This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture. |
dgisselq |
3276d 19h |
/zipcpu/trunk/doc/src/spec.tex |
| 68 |
Updated specification, includes well illustrated pipeline discussion. |
dgisselq |
3311d 20h |
/zipcpu/trunk/doc/src/spec.tex |
| 39 |
Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked. |
dgisselq |
3360d 17h |
/zipcpu/trunk/doc/src/spec.tex |
| 37 |
Fixed some minor spelling errors. |
dgisselq |
3369d 10h |
/zipcpu/trunk/doc/src/spec.tex |
| 36 |
*Lots* of changes to increase processing speed and remove pipeline stalls.
Removed the useless flash cache, replacing it with a proper DMA controller.
"make test" in the main directory now runs a test program in Verilator and
reports on the results. |
dgisselq |
3369d 22h |
/zipcpu/trunk/doc/src/spec.tex |
| 33 |
Finally finished a first draft of the full specification! |
dgisselq |
3398d 15h |
/zipcpu/trunk/doc/src/spec.tex |
| 32 |
Updated the document to match the most recent changes to the CPU. Specifically,
these include the re-instatement of the full SUB command with immediate offset,
and ... others I cannot remember.
The new document also describes what conditions create pipeline stalls,
together with how many cycles each stall condition will create. |
dgisselq |
3398d 23h |
/zipcpu/trunk/doc/src/spec.tex |
| 24 |
Lots more changes to the spec. It's still not done, but it is more complete
than before. |
dgisselq |
3402d 00h |
/zipcpu/trunk/doc/src/spec.tex |
| 23 |
Oops -- left some portions of the RTC Clock spec in with the ZIP CPU spec.
These were quickly removed. |
dgisselq |
3403d 20h |
/zipcpu/trunk/doc/src/spec.tex |
| 22 |
|
dgisselq |
3403d 20h |
/zipcpu/trunk/doc/src/spec.tex |
| 21 |
This update adds an incomplete version of the specification for the chip.
I ned to come back to this and do a lot more writing, but it is a start. |
dgisselq |
3403d 20h |
/zipcpu/trunk/doc/src/spec.tex |
