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[/] [System09/] - Rev 212

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Rev Log message Author Age Path
212 Switched from VGA output to HDMI output. davidgb 610d 19h /System09/
211 New version of VDU8 that has HDMI output. Still needs work refactoring clock signals. davidgb 610d 19h /System09/
210 Check in code fragment implementing HDMI/TMDS encoding.
Derived from HDMI_test.v https://www.fpga4fun.com/HDMI.html (c) fpga4fun.com & KNJN LLC 2013
davidgb 610d 19h /System09/
209 Started adding in keyboard (not tested).
Added in green-only VGA output thru Pmod port to PmodVGA J2 port.
Started working on HDMI output
davidgb 610d 21h /System09/
208 swapped 32k and 16k ram to use block_spram. davidgb 654d 22h /System09/
207 Updated design to pick up vdu8_spram (which uses parameterized ram for video memory instead of hard macros) davidgb 654d 22h /System09/
206 Update comment/cleanup davidgb 654d 22h /System09/
205 A new version of VDU8 that uses the parameterized xilinx ram "block_spram" for the video memory. davidgb 654d 22h /System09/
204 patched up ram for zybo use davidgb 654d 22h /System09/
203 Added a parameterized ram model. davidgb 654d 22h /System09/
202 Updated Zybo design to reintroduce VDU8 driving the PmodVGA on pmod connectors JC+JD.
This version also uses PmodUSBUART on JE. To use PmodRS232 you must edit the .ucf file and select the appropriate pin LOCs.
davidgb 654d 23h /System09/
201 A copy of XSA-3S1000.ucf and System09_Xess_XSA-3S1000.vhd that have dual serial ports with no handshake. davidgb 661d 18h /System09/
200 Started adding back in video support - VDU8 instantiated and RGBHV bits sent to Pmod JE port. davidgb 668d 15h /System09/
199 Add in full RS-232 handshake for PmodUSBUART. davidgb 669d 17h /System09/
198 Update UCF file to select Pmod pinout compatible with the PmodUSBUART.
To use, make sure PmodUSBUART has JP1 as "LCL". Connect the usb to the uart and open the terminal program. Test the transmission via the LED on the Pmod. Then (carefully) plug into Pmod port on Zybo.
davidgb 669d 18h /System09/
197 Updates from John Kent:
-- 4.5 John Kent 2012-02-04 Re-arranged Rx & Tx Baud clock edge detect.
-- 4.6 John Kent 3021-01-30 Double sample RxC, TxC, and RxD with cpu_clk
-- for 125MHz Clock on Zybo Z7 board.
davidgb 676d 15h /System09/
196 Working system boots to SBUG. Uses RS232 Pmod (no handshake) and 57600,8,N,1 (no handshake) hyperterm. davidgb 676d 15h /System09/
195 Switched to using the UART over usb for the console port. davidgb 676d 16h /System09/
194 Finally have a working board. davidgb 676d 16h /System09/
193 Fixed part of the ACIA problem - the polarity of the NMI was wrong. Now get clean output but input to the ACIA is not working. Also fixed the 32k addressing davidgb 676d 20h /System09/

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