OpenCores

URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.xise] - Rev 185

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
185	Reverted back to the single-step version - something was broken	davidgb	1182d 20h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
175	Corrected RS-232 pin connections. Cleaned up code. Removed debug code. System boots but the baud clock must be wrong - get garbage on hyperterm.	davidgb	1183d 10h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
174	Added button debounce. Single-step button. multiplex LED to show nibbles of addr and data for debug. Confirmed that CPU is reading from sys09swt.vhd SBug ROM correctly. Still need to debug ACIA output.	davidgb	1183d 14h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
173	Add another 16k BRAM for 56K total memory	davidgb	1185d 09h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
170	More debugging. Can now see cpu_addr incrementing correctly. Added 32k BRAM 0000-7FFF.	davidgb	1185d 15h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
158	switch to stock SWT boot rom and flex9ram	davidgb	1186d 15h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
152	More atlys cleanup	davidgb	1430d 01h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
148	Check in Atlys work	davidgb	1430d 01h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
146		davidgb	1431d 14h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
141	Started work on version for Digilent Atlys SPARTAN6 board (does not build, just infrastructure to start the project)	davidgb	1465d 18h	/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.