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[/] [System09/] [trunk/] [rtl/] [VHDL/] - Rev 198

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Rev Log message Author Age Path
197 Updates from John Kent:
-- 4.5 John Kent 2012-02-04 Re-arranged Rx & Tx Baud clock edge detect.
-- 4.6 John Kent 3021-01-30 Double sample RxC, TxC, and RxD with cpu_clk
-- for 125MHz Clock on Zybo Z7 board.
davidgb 1153d 07h /System09/trunk/rtl/VHDL/
139 format davidgb 1443d 12h /System09/trunk/rtl/VHDL/
138 Remove DOS format davidgb 1443d 13h /System09/trunk/rtl/VHDL/
130 updated cpus & mul/div dilbert57 2146d 03h /System09/trunk/rtl/VHDL/
122 dilbert57 4553d 21h /System09/trunk/rtl/VHDL/
118 Update components to be compatible with Terasic DE1 implementation dilbert57 4884d 01h /System09/trunk/rtl/VHDL/
100 Updates from John. Digilent S3STARTER and XSA-3S1000 work. davidgb 4949d 03h /System09/trunk/rtl/VHDL/
99 Updates from John. Digilent S3STARTER and XSA-3S1000 work. davidgb 4949d 04h /System09/trunk/rtl/VHDL/
66 New directory structure. root 5496d 23h /System09/trunk/rtl/VHDL/
65 added new files davidgb 5504d 11h /System09/trunk/rtl/VHDL/
22 Updated software - XSA-3S1000 now runs FLEX on an IDE drive or CF card. dilbert57 5857d 16h /System09/trunk/rtl/VHDL/
19 New directory structure dilbert57 5953d 16h /System09/trunk/rtl/VHDL/

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