OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [VHDL/] - Rev 199

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
197 Updates from John Kent:
-- 4.5 John Kent 2012-02-04 Re-arranged Rx & Tx Baud clock edge detect.
-- 4.6 John Kent 3021-01-30 Double sample RxC, TxC, and RxD with cpu_clk
-- for 125MHz Clock on Zybo Z7 board.
davidgb 1175d 15h /System09/trunk/rtl/VHDL/
139 format davidgb 1465d 20h /System09/trunk/rtl/VHDL/
138 Remove DOS format davidgb 1465d 20h /System09/trunk/rtl/VHDL/
130 updated cpus & mul/div dilbert57 2168d 11h /System09/trunk/rtl/VHDL/
122 dilbert57 4576d 05h /System09/trunk/rtl/VHDL/
118 Update components to be compatible with Terasic DE1 implementation dilbert57 4906d 08h /System09/trunk/rtl/VHDL/
100 Updates from John. Digilent S3STARTER and XSA-3S1000 work. davidgb 4971d 11h /System09/trunk/rtl/VHDL/
99 Updates from John. Digilent S3STARTER and XSA-3S1000 work. davidgb 4971d 11h /System09/trunk/rtl/VHDL/
66 New directory structure. root 5519d 07h /System09/trunk/rtl/VHDL/
65 added new files davidgb 5526d 19h /System09/trunk/rtl/VHDL/
22 Updated software - XSA-3S1000 now runs FLEX on an IDE drive or CF card. dilbert57 5880d 00h /System09/trunk/rtl/VHDL/
19 New directory structure dilbert57 5976d 00h /System09/trunk/rtl/VHDL/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.