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[/] [System09/] [trunk/] [rtl/] [VHDL/] [acia6850.vhd] - Rev 197


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Rev Log message Author Age Path
197 Updates from John Kent:
-- 4.5 John Kent 2012-02-04 Re-arranged Rx & Tx Baud clock edge detect.
-- 4.6 John Kent 3021-01-30 Double sample RxC, TxC, and RxD with cpu_clk
-- for 125MHz Clock on Zybo Z7 board.
davidgb 971d 15h /System09/trunk/rtl/VHDL/acia6850.vhd
139 format davidgb 1261d 21h /System09/trunk/rtl/VHDL/acia6850.vhd
138 Remove DOS format davidgb 1261d 21h /System09/trunk/rtl/VHDL/acia6850.vhd
118 Update components to be compatible with Terasic DE1 implementation dilbert57 4702d 09h /System09/trunk/rtl/VHDL/acia6850.vhd
100 Updates from John. Digilent S3STARTER and XSA-3S1000 work. davidgb 4767d 12h /System09/trunk/rtl/VHDL/acia6850.vhd

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