OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] - Rev 216

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
216 Get rid of warning about unconnected CLK0 pin davidgb 1109d 16h /
215 Update project after switching to xilinx block ram davidgb 1109d 19h /
214 Switch to Xilinx block ram davidgb 1109d 19h /
213 updated project file davidgb 1109d 19h /
212 Switched from VGA output to HDMI output. davidgb 1109d 19h /
211 New version of VDU8 that has HDMI output. Still needs work refactoring clock signals. davidgb 1109d 19h /
210 Check in code fragment implementing HDMI/TMDS encoding.
Derived from HDMI_test.v https://www.fpga4fun.com/HDMI.html (c) fpga4fun.com & KNJN LLC 2013		 davidgb 1109d 19h /
209 Started adding in keyboard (not tested).
Added in green-only VGA output thru Pmod port to PmodVGA J2 port.
Started working on HDMI output		 davidgb 1109d 21h /
208 swapped 32k and 16k ram to use block_spram. davidgb 1153d 22h /
207 Updated design to pick up vdu8_spram (which uses parameterized ram for video memory instead of hard macros) davidgb 1153d 23h /
206 Update comment/cleanup davidgb 1153d 23h /
205 A new version of VDU8 that uses the parameterized xilinx ram "block_spram" for the video memory. davidgb 1153d 23h /
204 patched up ram for zybo use davidgb 1153d 23h /
203 Added a parameterized ram model. davidgb 1153d 23h /
202 Updated Zybo design to reintroduce VDU8 driving the PmodVGA on pmod connectors JC+JD.
This version also uses PmodUSBUART on JE. To use PmodRS232 you must edit the .ucf file and select the appropriate pin LOCs.		 davidgb 1154d 00h /
201 A copy of XSA-3S1000.ucf and System09_Xess_XSA-3S1000.vhd that have dual serial ports with no handshake. davidgb 1160d 18h /
200 Started adding back in video support - VDU8 instantiated and RGBHV bits sent to Pmod JE port. davidgb 1167d 16h /
199 Add in full RS-232 handshake for PmodUSBUART. davidgb 1168d 17h /
198 Update UCF file to select Pmod pinout compatible with the PmodUSBUART.
To use, make sure PmodUSBUART has JP1 as "LCL". Connect the usb to the uart and open the terminal program. Test the transmission via the LED on the Pmod. Then (carefully) plug into Pmod port on Zybo.		 davidgb 1168d 19h /
197 Updates from John Kent:
-- 4.5 John Kent 2012-02-04 Re-arranged Rx & Tx Baud clock edge detect.
-- 4.6 John Kent 3021-01-30 Double sample RxC, TxC, and RxD with cpu_clk
-- for 125MHz Clock on Zybo Z7 board.		 davidgb 1175d 16h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.