URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] - Rev 11

Rev	Log message	Author	Age	Path
11	Corrected a small problem with the KAT testbench.	motilito	4001d 07h	/aes_highthroughput_lowarea/
10	Minor documentation bug fix.	motilito	4362d 18h	/aes_highthroughput_lowarea/
9	Corrected block diagram with the size of i_key_mode input signal.	motilito	4401d 19h	/aes_highthroughput_lowarea/
8	Added core specification document, core top example module and FPGA synthesis project files.	motilito	4402d 06h	/aes_highthroughput_lowarea/
7	Added AES KAT test bench and simulation batch files for Icarus Verilog. Note that reset polarity was changed to rising edge (posedge).	motilito	4857d 04h	/aes_highthroughput_lowarea/
6	Correcting some problems with bench directory	motilito	4857d 08h	/aes_highthroughput_lowarea/
5	Updating sub-directory structure	motilito	4857d 08h	/aes_highthroughput_lowarea/
4	Moving RTL to verilog sub-directory	motilito	4857d 09h	/aes_highthroughput_lowarea/
3	Building new directory structure.	motilito	4857d 18h	/aes_highthroughput_lowarea/
2	initial release	rainrhythm	5159d 01h	/aes_highthroughput_lowarea/
1	The project and the structure was created	root	5161d 11h	/aes_highthroughput_lowarea/