URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32.v] - Rev 44

Rev	Log message	Author	Age	Path
44	Add single step support	ultra_embedded	3637d 02h	/altor32/trunk/rtl/cpu/altor32.v
40	- Add support for 2 way instruction cache (not yet enabled) - Bug fixes and tidy up	ultra_embedded	3651d 06h	/altor32/trunk/rtl/cpu/altor32.v
37	- Add icarus sim test - Adopt consistent naming scheme - Simplify instruction cache	ultra_embedded	3665d 10h	/altor32/trunk/rtl/cpu/altor32.v
36	Various performance improvements and bug fixes.	ultra_embedded	3670d 23h	/altor32/trunk/rtl/cpu/altor32.v
32	Switch memory interfaces to Wishbone (pipelined). Various bug fixes and improvements.	ultra_embedded	3764d 03h	/altor32/trunk/rtl/cpu/altor32.v
27	Initial drop of AltOR32 v2	ultra_embedded	3869d 03h	/altor32/trunk/rtl/cpu/altor32.v