URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_exec.v] - Rev 40

Rev	Log message	Author	Age	Path
40	- Add support for 2 way instruction cache (not yet enabled) - Bug fixes and tidy up	ultra_embedded	3643d 12h	/altor32/trunk/rtl/cpu/altor32_exec.v
39	Bug fix interrupt handling after last update.	ultra_embedded	3648d 08h	/altor32/trunk/rtl/cpu/altor32_exec.v
37	- Add icarus sim test - Adopt consistent naming scheme - Simplify instruction cache	ultra_embedded	3657d 17h	/altor32/trunk/rtl/cpu/altor32_exec.v
36	Various performance improvements and bug fixes.	ultra_embedded	3663d 06h	/altor32/trunk/rtl/cpu/altor32_exec.v
32	Switch memory interfaces to Wishbone (pipelined). Various bug fixes and improvements.	ultra_embedded	3756d 10h	/altor32/trunk/rtl/cpu/altor32_exec.v
31	Improvements to the execute stage logic.	ultra_embedded	3776d 10h	/altor32/trunk/rtl/cpu/altor32_exec.v
27	Initial drop of AltOR32 v2	ultra_embedded	3861d 09h	/altor32/trunk/rtl/cpu/altor32_exec.v