URL https://opencores.org/ocsvn/cop/cop/trunk

Subversion Repositories cop

[/] [cop/] [trunk/] [rtl/] [verilog/] [cop_wb_bus.v] - Rev 12

Rev	Log message	Author	Age	Path
12	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5200d 06h	/cop/trunk/rtl/verilog/cop_wb_bus.v
8	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5408d 08h	/cop/trunk/rtl/verilog/cop_wb_bus.v
2	Initial Release June 16, 2009 - Bob Hayes	rehayes	5425d 07h	/cop/trunk/rtl/verilog/cop_wb_bus.v